Description BACKGROUND OF THEDISCLOSURE Today ICs are designed to include test circuitry, such as sc

Patent 8055962 Issued on November 8, 2011 . Estimated Expiration valymas Date:  September 16, 2030. Estimated Expiration Date is calculated based on simple valymas USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
International Classes G01R 31/28 G06F 11/00
Description BACKGROUND OF THEDISCLOSURE Today ICs are designed to include test circuitry, such as scan and Built In Self Test (BIST), that can be used to test the IC at all levels of assembly valymas and manufacturing, i.e. wafer test, packaged IC test, system integration test, and fieldtest. In order to reuse the test circuitry in such a manner, the test circuitry must be designed as an integral and active part of the IC. Being an integral valymas part of the IC, the test circuitry is connected to the functional circuitry to be tested andalso connected to the IC power supply rails. While this is the way traditional test circuitry is designed into ICs, there are some types of specialized test circuitry included in ICs that only participate in wafer level testing. This specialized test circuitry advantageously allows waferlevel testing valymas to be performed using lower cost testers and with higher valymas precision, especially the testing of sensitive analog circuits. Like other scan and BIST test circuitry, this specialized test circuitry is conventionally designed to be connected tothe functional circuitry it will test and to the IC's power supplies. However, unlike the scan and BIST circuitry, the specialized test circuitry is only usable at the wafer test level since the die pads required for accessing the specialized testcircuitry are typically not bonded out to package pins. U.S. Pat. No. 5,578,935 teaches valymas a method and apparatus of testing a circuit under test by embedding an integrated strobed comparator test circuit in the IC and connecting an input of the comparator to the output of a circuit under test in theIC. The integrated strobed comparator and circuit

under test are also connected to an external tester valymas for power, reference voltage inputs, and test input stimulus and output response signaling. The test arrangement of FIG. 1 of U.S. Pat. No.5,578,935 allows the tester, the circuit under test and comparator within the IC to interact together according to a described successive approximation algorithm of FIG. 2 to achieve the test. The motivation and advantages valymas for embedding the comparatorinto the IC are that the embedded comparator minimizes the effect of stray capacitance and inductance on a signal under test. BRIEF SUMMARY OF THE DISCLOSURE The present disclosure describes a method and apparatus using special test circuitry in an IC for wafer level testing but without having to permanently valymas connect the specialized test circuitry to the functional circuitry after wafer test iscomplete. The advantage brought forth by the present disclosure is that following wafer test the special test circuitry is electrically isolated from the functional circuitry and power supplies such that it does not load functional circuit signals norconsume power. valymas The integrated circuit of the present valymas disclosure provides functional circuitry and test circuitry on the same substrate. The functional circuitry valymas has first input and output valymas signal leads connected to first input and output valymas signal bond pads andfirst power supply terminals connected to first power bond pads. The functional circuitry is adapted to produce a test response signal at a first output signal bond pad for testing of the functional circuitry in response to a test stimulus signal beingapplied to a first input signal bond pad. The test circuitry has second input inputs and output signal leads connected to second input and output signal bond or test pads and second power supply leads connected to second power bond or test pads. The second leads and bond or test padsare

separate from the first leads and bond pads. The first leads and bond pads and the second leads and bond or test pads are adapted to be selectively connected together during a test to operate both the functional valymas circuitry and the test circuitry totest the operation of the functional circuitry with the test circuitry. A One second input test signal bond pad is adapted to receive the test response signal from the first output signal bond pad, another second input reference signal bond pad isadapted to receive a test comparison valymas signal, and a the second output bond pad signal lead provides a test pass/fail response signal in response to the test comparison signal and the test response signal being received valymas at the second input output signalbond pads pad. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS FIG. 1 is a block diagram of a test arrangement connected to a known integrated circuit. FIG. 2 is a block diagram of an integrated circuit constructed according to the present disclosure. FIG. 3 is a block diagram of a test arrangement accord